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document number: mc33800 rev. 5.0, 10/2007 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2007. all rights reserved. engine control integrated circuit the 33800 is a combination output switch and driver integrated circuit (ic) which can be used in numerous powertrain applications. the ic contains two programmable constant current drivers (ccd), an octal, low side, serial switch (oss), and six, external mosfet gate pre-drivers (gd). the ic has over-voltage, under-voltage, and thermal protection. all drivers an d switches, including the external mosfets, have over-current protection, off- state open load detection, on-state shorted load de tection, and fault annunciation via the serial peripheral interface (spi). additional features include: low power sleep mode, heated exhaust gas oxygen (hego) sensor diagnostics, output control via serial and/or parallel inputs, pwm capability, and programmable current output with dithering. these features, along with cost effective packaging, make the 33800 ideal for powertrain engine control applications. features ? wide operating voltage range, 5 < vpwr < 36v ? interfaces to 3.3v and 5v microprocessors via spi protocol ? low, sleep mode, standby current, typically 10ua. ? internal or external voltage reference ? internal oscillator with calibrate capability ? measures resistance to monitor hego sensors ? ccds have programmable current, dither frequency and amplitude ? osss can be paralleled to increase current capability ? gds have programmable fr equency and duty cycle pwm ? all outputs controllable via serial and/or parallel inputs ? pb-free packaging designated by suffix code ek figure 1. mc33800 simplified application diagram engine control ek suffix (pb-free) 98asa99334d 54-pin soicw-ep 33800 ordering information device temperature range (t a ) package mcz33800ek/r2 -40c to 125c 54 soicw ep vdd vpwr default v dd si so sclk cs mosi miso an0 out1 33800 sclk cs gnd v bat out8 ccd1_out ccd2_out v pwr v bat v bat vdsns1 gd1 gd6 pwm1 pwm6 ccd1_rec ccd2_rec mcu vcal rext ri_ref lrfdbk p1,p3,p5,p7 2.5v vdsns6 en { { vssns456 vssns123 v pwr
analog integrated circuit device data 2 freescale semiconductor 33800 internal block diagram internal block diagram figure 2. 33800 simplifi ed internal block diagram vpwr, vdd por oscillator bandgap sleep pwr p1 gate control open/short + pgnd r s llimit 53v ? outputs 1 to 8 out 1 to out 8 si sclk cs so v pwr vdsns4 vssns456 gd4 + ? rext lrfdbk predriver4,5,6 logic control & spi interface gate control open/short + ccgnd r s llimit 53v ? ccd2 outputs ccd2_out ccd2_rec en vcal ccd1 outputs ccd1_rec ccd1_out ccgnd + ? + ? vcal default v pwr vdsns1 vssns123 gd1 predriver1,2,3 vpwr vdd gnd + ? vcal ri_ref exposed pad 40 a 80 a p3 15 a p5 15 a p7 15 a 15 a 15 a v dd 15 a 15 a v dd pwm1 15 a pwm2 15 a pwm3 15 a pwm4 15 a pwm5 15 a pwm6 15 a 75 a differential amplifier 15 a pgnd pgnd gate drive control & diagnostics gate drive control & diagnostics 100k
analog integrated circuit device data freescale semiconductor 3 33800 pin connections pin connections figure 3. 33800 pin connections table 1. 33800 pin definitions a functional description of each pin can be found in the functional pin description section beginning on page 16 . pin number pin name pin function formal name definition 1, 3, 5, 50, 52, 54 vdsns1- vdsns6 input drain voltage sense the vdsns pin is used to monitor the drain voltage of the external mosfet. 2, 4, 6, 49, 51, 53 gd1-gd6 output gate driver output the gd pin provides gate drive for an external mosfet 7 48 vssns456 vssns123 input source voltage sense the vssns pins are used to monitor th e source voltage of the external mosfets. 8 lrfdbk output load resistance feedback the lrfdbk pin is an operational amplifier output. 9 si input serial input data the si input pin is used to receive se rial data from the mcu. the serial input data is latched on the rising edge of sclk, and the input data transitions on the falling edge of sclk. 10 sclk input serial clock input the sclk input pin is used to clock in and out the serial data on the si and so pins while being addressed by the cs . 11 cs input chip select the chip select input pin is an active low signal sent by the mcu to indicate that the device is being addr essed. this input requires cmos logic levels and has an internal active pull up current source. 12 p1 input input one input control of oss output 1. when configured via the spi, p1 input may be used to control oss output 1 and output 2 in parallel. 13 p3 input input three input control of oss output 3. when configured via the spi, p3 input may be used to control oss output 3 and output 4 in parallel. 14 p5 input input five input control of oss output 5. when configured via the spi, p5 input may be used to control oss output 5 and output 6 in parallel. 54 40 35 34 33 32 31 30 29 28 39 38 37 36 47 46 45 44 43 42 41 51 50 49 48 53 52 1 15 20 21 22 23 24 25 26 27 16 17 18 19 8 9 10 11 12 13 14 4 5 6 7 2 3 vdsns4 gd4 vdsns5 gd5 vdsns6 gd6 vssns456 lrfdbk si sclk cs p1 p3 p5 p7 pwm1 pwm2 pwm3 pwm4 pwm5 pwm6 ccd2_gnd ccd2_out ccd2_rec en ri_ref ccd1_out vdsns3 gd3 vdsns2 gd2 vdsns1 gd1 vssns123 rext pgnd1 out1 pgnd2 out2 out3 out4 out5 pgnd out6 out7 out8 default so vdd vcal gnd vpwr ccd1_gnd ccd1_rec
analog integrated circuit device data 4 freescale semiconductor 33800 pin connections 15 p7 input input seven input control of oss output 7. when configured via the spi, p7 input may be used to control oss output 7 and output 8 in parallel. 16,17, 18, 19, 20, 21 pwmx input pulse width modulated input the pwmx input pin is used for dire ct parallel control of the gdx (gate drive output x) predriver or as on/off control of the internal pwm controller. control strategy is programmed via the spi. 22 ccd2_gnd ground ccd2 ground the ccd2_gnd pin provides a dedicated ground for the ccd2 constant current controller 23 ccd2_out output current controlled driver 2 output the ccd2_out pin is connected to a se ries internal sense resistor and power mosfet driver. the ccd2_out has a pull up and pull down current source and is used for fault threshold monitoring. 24 ccd2_rec input current controlled driver 2 recirculation input the ccd2_rec pin provides a recirc ulation path for the load current. the ccd2_rec pin is connected to the node between the internal sense resistor and power mosfet driver. the device uses the differential voltage between ccd2_rec and ccd2_out to determine the load solenoid current. 25 en input enable the en pin is an active high input. 26 ri_ref output resistor for current reference the ri_ref pin is used to generate a reference current. the reference is used in the regulation of the cons tant current controller. the constant current controller regulation current is inversely proportional to the reference current through the external resistor. a 39.2k ? 1% resistor to ground will set the 1ff programmed current value of the ccd1 to 1075ma and the ccd2 to be 232ma. 27 ccd1_out output current controlled driver 1 output the ccd1_out pin is connected to a se ries internal sense resistor and power mosfet driver. the ccd1_out has a pull up and pull down current source and is used for fault threshold monitoring. 28 ccd1_rec input current controlled driver 1 recirculation input the ccd1_rec pin provides a recirc ulation path for the load current. the ccd1_rec pin is connected to the node between the internal sense resistor and power mosfet driver. the device uses the differential voltage between ccd1_rec and ccd1_out to determine the load solenoid current. 29 ccd1_gnd ground ccd1 ground the ccd1_gnd pin provides a dedicated ground for the ccd1 constant current controller 30 vpwr power input analog voltage supply the vpwr pin provides power to all pr e-driver, driver and output circuits and other internal functions such as the oscillator and spi circuits. 31 gnd ground ground analog ground for the internal control circuits of the ic. this ground should be used for decoupli ng of vdd and vpwr supply. 32 vcal input voltage calibrated input vcal input is a precision (2.5v, +8.0mv, -20mv over temperature) reference input, used in several internal circuits. a 1.0nf to 10nf decoupling capacitor is required on the vcal input pin to ground. 33 vdd power input digital voltage supply the vdd pin supplies power to the serial output (so) buffer along with the pull up current sources for the chip select ( cs ) and default inputs. 34 so output serial output data the so output pin is used to transmit serial data from the device to the mcu. the so pin remains tri-stated until selected by the active low cs . the serial output data is available to be latched by the mcu on the rising edge of sclk. the so data transitions on falling edge of the sclk. 35 default input default mode enable the default pin is an active high input. 36-38, 40, 41-43, 45 out1-out8 output oss output 1-8 octal serial switch (oss) low side driver output 1-8. table 1. 33800 pin de finitions(continued) a functional description of each pin can be found in the functional pin description section beginning on page 16 . pin number pin name pin function formal name definition
analog integrated circuit device data freescale semiconductor 5 33800 pin connections 39 pgnd3 ground oss 3-8 ground this pgnd pins provide a dedicated ground for the octal serial switch (oss) low side driver outputs 3 - 8. 44 pgnd2 ground oss 2 ground this pgnd pin provides a dedicated gr ound for the octal serial switch (oss) low side driver output 2. 46 pgnd1 ground oss 1 ground this pgnd pin provides a dedicated gr ound for the octal serial switch (oss) low side driver output 1. 47 rext output resistor external reference the rext pin is used to generate a reference current. _ _ ground exposed pad ground the package exposed pad provides t hermal conductivity for the die and should be grounded to system ground. table 1. 33800 pin de finitions(continued) a functional description of each pin can be found in the functional pin description section beginning on page 16 . pin number pin name pin function formal name definition
analog integrated circuit device data 6 freescale semiconductor 33800 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings supply voltage v pwr v dd v pwr v dd -1.5 to 45 -0.3 to 7.0 v dc cs , si, so, sclk, en, default, pwmx, p1, p3, p5, p7 ? -0.3 to v dd v dc predriver drain voltage (vdsns1 to vdsns6) v dsns -0.3 to 60 v dc oss output clamp energy (o ut3 to out8)(single pulse) t junction = 150c, i out = 0.45a e clamp 30 mj oss output clamp energy (out1 & out2)(single pulse) t junction = 150c, i out = 0.45a e clamp 45 mj ccd1 output clamp energy (single pulse) t junction = 150c, i out = 0.45a e clamp 75 mj ccd2 output clamp energy (single pulse) t junction = 150c, i out = 0.45a e clamp 25 mj oss output continuous current (out1 to out8 steady state) t junction = 150c i oss_ss 350 ma ccd1 output clamp energy (ccd1_rec output) t junction = 150c, i out = 1.0 a e clamp 75 mj frequency of spi operation (v dd = 5.0v) (3) ? 4.0 mhz esd voltage (1) human body model machine model v esd1 v esd2 2000 200 v thermal ratings storage temperature t stg -55 to 150 c operating case temperature t c -40 to 125 c operating junction temperature t j -40 to 150 c power dissipation (t a = 25 c) (2) p d 1.7 w thermal resistance thermal resistance junction to ambient between the die and the exposed die pad r ja r jc 71 1.2 c/w notes 1. esd data available upon request. all pins te sted individually. esd1 testing is perform ed in accordance with the human body mo del (aec-q100-002). and the machine model (aec-q100-003). 2. maximum power dissipation at t j =150 c junction temperature with no heat sink used. 3. this parameter is guaranteed by design but is not production tested.
analog integrated circuit device data freescale semiconductor 7 33800 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electric al characteristics characteristics noted under conditions 3.0v v dd 5.5v, 9.0v v pwr 18v, - 40 c t a 125 c, gnd = 0v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit power input (vpwr, vdd) supply voltage fully operational v pwr (fo) 5.0 ? 36 v supply current all outputs disabled (normal & default mode) i pwr (on) ? 10.0 14.0 ma sleep state supply current v dd 0.8 v, v pwr = 18v en 0.8 v, v dd = 5.5v i pwr ( ss ) i vdd (ss) ? ? 10 2.0 30 5.0 a v pwr over-voltage shutdown threshold voltage (4) v pwr( ov) 36.5 39 44 v v pwr over-voltage shutdown hysteresis voltage v pwr( ovhys) 0.5 1.5 3.0 v v pwr under-voltage shutdown threshold voltage (5) v pwr( uv) 3.0 4.0 4.4 v v pwr under-voltage shutdown hysteresis voltage v pwr( uvhys) 100 200 650 mv logic supply voltage v dd 3.0 ? 5.5 v logic supply current static condition i dd 180 300 525 a logic supply under-voltage shutdown threshold voltage (5) v dd(uv) 0.8 2.5 2.8 v logic supply under-voltage hysteresis v dd(uvhys) 100 ? 650 mv internally generated v cal (6) v bias 2.2 2.5 2.8 v constant current solenoid driver output (ccd1_out) drain-to-source on resistance t j = 125 c, v pwr = 13v t j = 25 c, v pwr = 13v t j = -40 c, v pwr = 13v rds(on) ? ? ? ? 0.25 ? 0.60 ? ? ? internal current sense resistor dac value = 000, v ccd1rec = 0.0v, i ccd1out = 100ma r sense = v ccd1out / i ccd1out r sense 0.7 1.2 ? current regulation dac value = 17c hex +/- (3%) dac value = 05f hex +/- (15%) load resistance = 5 ?, load inductance = 10mh, dither off i ccd1 775 157 800 200 823 235 ma programmable dither frequency programmable from 50hz to 500hz in 50hz increments after calibration f dither -10 10 % notes 4. over-voltage thresholds minimu m and maximum include hysteresis. 5. under-voltage thresholds minimu m and maximum include hysteresis. 6. using the internally generated v cal increases all applicable par ametric tables by +- 10%
analog integrated circuit device data 8 freescale semiconductor 33800 electrical characteristics static electrical characteristics constant current solenoid driver output (cdd1_out) (continued) programmable dither amplitude peak to peak programmable from 0.0ma to 350ma in 50ma increments i dither -10 10 % ccd1 fault detection voltage threshold outputs programmed off v out( fltth ) 2.0 2.5 3.0 v ccd1 output clamp voltage outputs programmed off v oc 50 55 60 v ccd1 output self limiting current i out (lim) 1.5 ? 2.8 a ccd1 output leakage current pull-up enabled, dither off, ccd1out = v oc - 1.0v pull-up enabled, dither off, ccd1out = v pwr = 24v i ccd1 (lkg) ? ? ? 8000 20 a ccd1 pull up current pull-up enabled, dac = 000, ccd1out = ccd1rec = 2.0v i ccd1( pullup ) -60 -40 -20 a ccd1 pull down current pull-up disabled, dac = 000, ccd1out = ccd1rec = 2.0v i ccd1( pulldown ) 20 40 60 a constant current solenoid driver output (ccd2_out) drain-to-source on resistance t j = 125 c, v pwr = 13v t j = 25 c, v pwr = 13v t j = -40 c, v pwr = 13v rdson ? ? ? ? 1.0 ? 2.0 ? ? ? internal current sense resistor dac value = 000, v ccd2rec = 0v, i ccd2out = 100ma r sense = v ccd2out / i ccd2out r sense 3.5 5.0 ? current regulation dac value = 17c hex +/- (4%) dac value = 05f hex +/- (10%) load resistance = 32 ?, load inductance = 130mh, dither off i ccd2 166 38.9 173 43.2 180 47.5 ma programmable dither frequency programmable from 50hz to 500hz in 50hz increments after calibration f dither -10 10 % programmable dither amplitude peak to peak programmable from 0.0ma to 90ma in 10.9ma increments i dither -10 10 % ccd2 fault detection voltage threshold outputs programmed off v out( fltth) 2.0 2.5 3.0 v ccd2 output clamp voltage outputs programmed off v oc 50 55 60 v ccd2 output leakage current pull-up enabled, dither off, ccd2out = v oc - 1.0v pull-up enabled, dither off, ccd2out = v pwr = 24v i ccd2 (lkg) ? ? ? 8000 20 a ccd2 output self limiting current i out (lim) 0.5 ? 1.0 a table 3. static elec trical characteristics characteristics noted under conditions 3.0v v dd 5.5v, 9.0v v pwr 18v, - 40 c t a 125 c, gnd = 0v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 9 33800 electrical characteristics static electrical characteristics constant current solenoid driver output (ccd2_out) (continued) ccd2 pull up current pull-up enabled, dac = 000, ccd1out = ccd1rec = 2.0v i ccd2( pullup) -60 -40 -20 a ccd2 pull down current pull-up disabled, dac = 000, ccd2out = ccd2rec = 2.0v i ccd2( pulldown ) 20 40 60 a octal serial drivers (out1 - 8) drain-to-source on resistance (out1 - 2) i out = 0.350a, t j = 125 c, v pwr = 13v i out = 0.350a, t j = 25 c, v pwr = 13v i out = 0.350a, t j = -40 c, v pwr = 13v r ds (on) ? ? ? ? 0.7 ? 1.4 ? ? ? drain-to-source on resistance (out3 - 8) i out = 0.350a, t j = 125 c, v pwr = 13v i out = 0.350a, t j = 25 c, v pwr = 13v i out = 0.350a, t j = -40 c, v pwr = 13v r ds (on) ? ? ? ? 1.0 ? 1.7 ? ? ? output self limiting current output 3 to output 8 output 1, output 2 i out (lim) 1.0 4.0 ? ? 2.0 6.0 a output fault detection voltage threshold. (7) outputs programmed off v out (fltth) 2.0 2.5 3.0 v output off open load detection current v drain = 18v, outputs programmed off i oco 40 75 100 a output clamp voltage low side drive i d = 20ma v oc 50 55 60 v output leakage current v dd = 5.0v, v drain = 24v, open load detection current disabled v dd = 5.0v, v drain = v oc - 1.0v, open load detection current disabled v dd = 0v, v drain = 24v, device disabled i out (lkg) ? ? ? ? ? ? 20 3000 10 a over-temperature shutdown (8) tlim 155 ? 185 c over-temperature shutdown hysteresis (8) tlim (hys) 5.0 10 15 c spi digital interface (so, si, cs , sclk) input logic high-voltage thresholds (8) v ih 0.7 x v dd ? v dd + 0.3 v input logic low-voltage thresholds (8) v il gnd - 0.3 ? 0.2 x v dd v input logic voltage hysteresis (8) v hys 100 ? 300 mv input logic capacitance (8) c in ? ? 20 pf sleep mode input logic current (8) v dd = 0.0v i lo gicss -10 ? 10 a notes 7. output fault detection thresholds with outputs programmed off. output fault detect thresholds are the same for output open an d shorts. 8. this parameter is guaranteed by design, however is not production tested. table 3. static elec trical characteristics characteristics noted under conditions 3.0v v dd 5.5v, 9.0v v pwr 18v, - 40 c t a 125 c, gnd = 0v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 10 freescale semiconductor 33800 electrical characteristics static electrical characteristics spi digital interface (so, si, cs , sclk) (continued) sleep mode en and default input current v d d = 0.0v, v en = 5.0v, v d e fa u lt = 5.0v i log icss -10 ? 10 a normal mode input logic pull-down current (9) 0.8v to 5.0v i lo gicpd 5.0 15 25 a normal mode default pull-up current i defaultpu -5.0 ? -25 a sclk, tri-state so output 0.0v to 5.0v i sclk, i triso -10 ? 10 a cs input current cs = v dd i cs -10 ? 10 a cs pull-up current cs = 0.0v i c s pu -5.0 ? -30 a cs leakage current to v dd cs = 5.0v, v dd = 0.0v i cs(lkg) ? ? 10 a so high-state output voltage i sohigh = -1.0ma v sohigh v dd - 0.4 ? ? v so low-state output voltage i solow = 1.0ma v solow ? ? 0.4 v en input pull-down current en = v dd i enpd 10 50 100 a predriver output function (gd1 - gd6) gate drive output voltage i gatedrive = 100 a i gatedrive = - 100 a v gs (on) v gs (off) 5.0 ? 7.0 0.2 9.0 0.5 v gate drive sink and source current i gatedrive ? 2.0 5.0 ma sleep mode gate to source resistor r gs (pulldown) 65 200 300 k ? short fault detection voltage threshold v dd = high, outputs programmed on programmable from 0.5v to 3.0v in 0.5v increments. v ds(fltth) -20% +20% v open fault detection voltage threshold v dd = high, outputs programmed off v ds(fltth) 2.0 2.5 3.0 v notes 9. parameter applies to p1, p3, p5, p7, pwm1 to pwm6, si and vcal, and are guaranteed by design. table 3. static elec trical characteristics characteristics noted under conditions 3.0v v dd 5.5v, 9.0v v pwr 18v, - 40 c t a 125 c, gnd = 0v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 11 33800 electrical characteristics static electrical characteristics predriver output function (gd1 - gd6) (continued) drain sense fault detection current gate drive off, vds = 18v i dsns(flt-sns) 40 180 400 a output clamp voltage driver command off, v gate = 2.0v v oc 50 55 60 v sleep mode drain sense leakage current v dd = 0.0v, v dsns = 24v, i dsns (lkg) ? ? 25 a load resistance feedback accuracy sample and hold after 150ms r ext = 24ohm, r load = 10ohm, lr fdbk = vcal*2.5*(r load /r ext ) lr fbckacc -10% 2.6 +10% v load resistance feedback output voltage (v dsns1 - v dsns2 ) 10v, pwm diagnostics select = 0001 lr fbckmax 6.0 v table 3. static elec trical characteristics characteristics noted under conditions 3.0v v dd 5.5v, 9.0v v pwr 18v, - 40 c t a 125 c, gnd = 0v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 12 freescale semiconductor 33800 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electri cal characteristics characteristics noted under conditions 3.0v v dd 5.5v, 9.0v v pwr 18v, - 40 c t a 125 c, gnd = 0v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit constant current solenoid driver output (ccd1_out) on state open load detect timer (10) fault is detected with driver on, timer expired t onopentimer 6.0 12 24 ms off state open load detect timer (10) fault detected with driver off & voltage threshold not achieved (driver off timer) t offopentimer 30 60 90 s on state shorted load detect timer (10) fault is detected with driver swit ching and drain voltage remains greater than threshold for specified time. t onshorttimer 30 60 90 s short retry time (10) t retry 10 14 24 ms output slew rate v bat = 14v, measured from 4.0v to 10.0v v bat = 14v, measured from 10.0v to 4.0v t sr(rise) t sr(fall) 2.0 -2.0 3.0 -3.0 4.0 -4.0 v/ s driver on time blanking period (10) t bp(off) 7.0 10 s driver off time blanking period (10) t bp(on) 7.0 10 s constant current solenoid driver output (ccd2_out) on state open load detect timer (10) fault is detected with driver on, timer expires (driver on timer) t onopentimer 6.0 12 24 ms off state open load detect timer (10) fault is detected with driver off and voltage threshold is not achieved. (driver off timer) t offopentimer 30 60 90 s on state shorted load detect timer (10) fault is detected with driver swit ching and drain voltage remains greater than threshold for specified time. t onshorttimer 30 60 90 s short retry time (10) t retry 10 14 24 ms output slew rate v bat = 14v, measured from 4.0v to 10.0v v bat = 14v, measured from 10.0v to 4.0v t sr(rise) t sr(fall) 1.5 -1.5 ? ? 4.0 -4.0 v/ s ccd2 dac update rate (10) response time from present current level to new programmed level t response 1.0 ms driver on time blanking period (10) t bp(on) 3.0 4.3 s driver off time blanking period (10) t bp(off) 12 17.2 s octal serial drivers (out1 - out8) output on current limit fault filter timer (10) t cl 30 50 90 s output refresh timer (10) t ref 5.0 10 15 ms output on short circuit fault filter timer (10) t sc 400 500 650 s notes 10. assumes oscillator has been cali brated using spi calibrate command.
analog integrated circuit device data freescale semiconductor 13 33800 electrical characteristics dynamic electrical characteristics octal serial drivers (out 1 - out8) (continued) output off open circuit fault filter timer (11) t oc 400 500 650 s output slew rate r load = 51 ? r load = 51 ? t sr(rise) t sr(fall) 1.0 1.0 5.0 5.0 10 10 v/ s p1 input propagation delay input @ 50% v dd to output voltage 10% of final value input @ 50% v dd to output voltage 90% of initial value t (risedelay) t (falldelay) 6.0 6.0 s p3, p5, p7 input propagation delay input @ 50% v dd to output voltage 10% of final value input @ 50% v dd to output voltage 90% of initial value t (risedelay) t (falldelay) 5.0 5.0 s oscillator and timer accuracy calibrated timer accuracy (11) t timer ? ? 10 % un-calibrated timer accuracy t timer ? ? 80 % spi digital interface timing (so, si, cs , sclk) (12) required low state duration on v pwr for reset (13) v pwr 0.2v t reset 1.0 ? ? s falling edge of cs to rising edge of sclk required setup time t lead 100 ? ? ns falling edge of sclk to rising edge of cs required setup time t lag 50 ? ? ns si to rising edge of sclk required setup time t si (su) 16 ? ? ns rising edge of sclk to si required hold time t si (hold) 20 ? ? ns si, cs , sclk signal rise time (14) t r (si) ? 5.0 ? ns si, cs , sclk signal fall time (14) t f (si) ? 5.0 ? ns time from falling edge of cs to so low-impedance (15) t so (en) ? ? 150 ns time from rising edge of cs to so high-impedance (16) t so (dis) ? ? 150 ns time from falling edge of sclk to so data valid (17) t valid ? 25 150 ns sequential transfer rate time required between data transfers t str 1.0 s notes 11. assumes oscillator has been cali brated using spi calibrate command 12. these parameters are guaranteed by design. production test equipment uses 1mhz, 5.0v spi interface. 13. this parameter is guaranteed by desi gn, however it is not production tested. 14. rise and fall time of incoming si, cs , and sclk signals for design consideration to prevent the occurrence of double pulsing. 15. time required for valid output status data to be available on so pin. 16. time required for output states data to be terminated at so pin. 17. time required to obtain valid data out from so following the fall of sclk with 200pf load. table 4. dynamic elec trical characteristics characteristics noted under conditions 3.0v v dd 5.5v, 9.0v v pwr 18v, - 40 c t a 125 c, gnd = 0v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 14 freescale semiconductor 33800 electrical characteristics dynamic electrical characteristics predriver output function (gd1 - gd6) open fault detection filter timer (18) v dd = high, outputs programmed off v ds(fltth) 100 128 400 s short fault detection filter timer (18) v dd = high, outputs programmed on programmable from 30 s to 960 s in replicating increments. t ds(flttmr) -10% +10% s gate drive rise slew rate cload = 1.0nf, vgs from 0.5 to 5.0v t gdsr(rise) ? 1.7 ? v/ s gate drive fall slew rate cload = 1.0nf, vgs from 5.0 to 0.5v t gdsr(fall) ? 1.7 ? v/ s pwm1 to pwm6 input propagation delay measured from pwm input at 4.5v and gdx output at 0.5v. t pwmdelay 20 300 ns load resistance feedback output rise slew rate c load = 40pf t lrsr(rise) 0.5 ? 2.0 v/ s load resistance feedback output fall slew rate c load = 40pf t lrsr(fall) 0.5 ? 2.0 v/ s load resistance sample duration (18) t loadsample 200 s load resistance feedback valid (18) time from rising edge of cs to load resistance measurement valid t fdbkvalid 400 us notes 18. assumes oscillator has been cali brated using spi calibrate command. table 4. dynamic elec trical characteristics characteristics noted under conditions 3.0v v dd 5.5v, 9.0v v pwr 18v, - 40 c t a 125 c, gnd = 0v, unless otherwise noted. typical values noted refl ect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 15 33800 electrical characteristics timing diagrams timing diagrams figure 4. spi timing characteristics t so(en) cs sclk si so msb out lsb out msb in 0.7 v dd 0.2 v dd 0.2 v dd 0.7 v dd t valid t so(dis) 0.7 v dd 0.2 v dd t lead 0.2 v dd t lag t si(su) t si(hold)
analog integrated circuit device data 16 freescale semiconductor 33800 functional description functional pin description functional description functional pin description analog voltage supply (vpwr) the vpwr pin is battery input to the 33800 ic. the vpwr pin requires external reverse bat tery and transient protection. maximum input voltage on vpwr is 45v. all ic analog current and internal logic current is provided from the vpwr pin. with v dd and en applied to the ic, the application of v pwr will perform a power-on reset ( por ). digital voltage supply (vdd) the vdd input pin is used to determine communication logic levels between the microprocessor and the 33800 device. current from v dd is used to drive so output and pull- up current for cs . v dd must be applied for normal mode operation. removing v dd from the ic will place the device in sleep mode. power-on reset will be performed with the application of v dd supply . ground (gnd) the gnd pin provides a low current analog ground for the ic. the vpwr and vdd supplies are both referenced to the gnd pin. gnd pin should be used for decoupling both supplies. constant current driver ground (ccdx_gnd) the constant current driv er ground (ccdx_gnd) pins provide dedicated grounds for t he constant current output drivers. both ccdx_gnd1 and ccdx_gnd2 grounds are isolated from the other grounds of the ic. ground (pgnd1 - 3, ccd1_gnd, ccd2_gnd) there are three pgnd pins associated with the oss drivers. out1 driver and out2 driver have dedicated pgnd1 & pgnd2 pins. drivers out3 through driver out8 share one pgnd3 pin. in gener al all ground pins must be connected together and terminated to ground on the circuit board. source voltage sense (vssns123 , vssns456) the source sense ground pins (vssns123, vssns456) provide dedicated grounds for the hex mosfet pre-drivers. the pins are used by the ic to monitor the drain to source voltage of the external mosfet . this pin must be connected to the source of the external mosfet and system ground. vssns123 and vssns456 ground pins are isolated from other internal ic grounds. serial clock input (sclk) the system clock (sclk) pin clocks the internal shift register of the 33800. the si data is latched into the input shift register on the rising edge of sclk signal. the so pin shifts status bits out on the falling edge of sclk. the so data is available for the mcu to read on the rising edge of sclk. with cs in a logic high state, signals on the sclk and si pins will be ignored and the so pin is tri-state. chip select ( cs ) the system mcu selects the 33800 to receive communication using th e chip select ( cs ) pin. with the cs in a logic low state, command words may be sent to the 33800 via the serial input (si) pin, and status information is received by the mcu via the serial output (so) pin. the falling edge of cs enables the so output and tr ansfers status information into the so buffer. rising edge of the cs initiates the following operation: 1. disables the so driver (high-impedance) 2. activates the received command word, allowing the 33800 to activate/deactivate output drivers. to avoid any spurious data, it is essential the high-to-low and low-to-high transitions of the cs signal occur only when sclk is in a logic low state. internal to the 33800 device is an active pull-up to vdd on cs . in cases were voltage exists on cs without the application of v dd , no current will flow from cs to the vdd pin. serial input data (si) the si pin is used for serial instruction data input. si information is latched into the input register on the rising edge of sclk. a logic high state present on si will program a one in the command word on the rising edge of the cs signal. to program a complete word, 16-bits of in formation must be entered into the device. serial output data (so) the so pin is the output from the shift register. the so pin remains tri-stated until the cs pin transitions to a logic low state. all normal operating drivers are reported as zero, all faulted drivers are reported as one. the negative transition of cs enables the so driver. the si / so shifting of the data follows a first-in-first-out protocol, with both input and ou tput words transferring the most significant bit (msb) first. enable (en) the enable pin is an active high digital input pin used to enable the device. with the en pin low the device is in sleep mode. with the en pin high, the device is in normal mode (v dd and v pwr applied). exit from sleep mode initiates a
analog integrated circuit device data freescale semiconductor 17 33800 functional description functional pin description power on reset (por). all internal registers will be placed in the reset state. the device has an internal 100 k ? resistor pull down on the enable pin. pulse width modulation (pwm) the pwm pins are control input pins for the mosfet pre- drivers. the pwm pins provide parallel control and can be programmed for an or function with the spi bit or an and function with the spi bit (see table 12, on page 25 for spi message detail). each pwm input pin has an internal 15 a pull down current source. the current sources are active when the device is in normal mode. drain voltage sense (vdsnsx) the vdsnsx pin has multiple functions for control and diagnostics of the external mosfet: 1. by monitoring the drain voltage of the external device, short circuits and open circuits are detected. the filter timer and threshold voltage are easily programmed through spi (see table 10, on page 23 and table 11, on page 24 for spi messages). 2. the vdsnsx pins are use to determine the external load resistance. further information is provided in the device operation section of this specification. 3. the vdsnsx pins provide a drain to gate clamp for fast turn off of inductive loads and mosfet protection. gate driver outputs (gdx) the gdx pins are the gate drive outputs for an external mosfets. internal to the device is a gate to source resistor designed to hold the external mosfet in the off state while the device is in por. inputs (p1, p3, p5, p7) the input pins for octal serial switch outputs 1,3,5,7. each input control pin has an internal pull down current source. two outputs may be controlled in parallel using the px pins ( see functional device operation on page 25 ). voltage calibrated input (vcal) the voltage calibrated input (v cal) provides the ic with a reference voltage for analog circuits. vcal (ext or int) must be applied for the ccd1 and ccd2 constant current controllers and load resistanc e measurement function to operate. for applications wh ere measurements are not critical, the vcal pin may grounded and an internally generated reference will be used. using the internally generated reference will add 10% to all tolerances in the parametric table. load resistance feedback (lrfdbk) the lrfdbk pin is an operational amplifier output. the amplifier output voltage is proportional to the load resistance for the selected channel. the channel is selected via the spi. default the default input controls t he operation of each driver to a default mode. the default input must be logic 0 for full function of all output driver s. for more information on the default operation ( see functional device operation on page 19 ). with the default pin high, the device is placed in default mode. the default pin is pulled up to the vdd supply through an active pull up current source. in default mode the device operates in the following manner: 1. oss outputs are disabled. 2. ccd1 and ccd2 outputs are disabled. 3. spi on/off control of gate drive (gd1 to gd6) outputs and on board pwm controllers are disabled. pwmx input control is enabled. in the default mode the device retains all register information and output status information. normal operation will resume when the default pin transitions low again and the device will operate as programmed prior to default mode. resistor external reference (rext) the reference current is used in the equation to calculate the load resistance of the pwm outputs. the load resistance measurement current is inversely proportional to rext current. the resistor value may be changed to adjust the load measurement current. a 24 ? resistor to ground sets the lrfdbk output to 260mv/ ? . exposed pad the silicon die is epoxy attached to the top side of the pad. although the device does not use the pad for electrical conduction, the bottom side exposed pad of the package should be grounded.
analog integrated circuit device data 18 freescale semiconductor 33800 functional description functional internal block description functional internal block description figure 5. functional block diagram analog control circuitry the 33800 is designed to operate from 5.0 to 36v on the vpwr pin. the vpwr pin supplies power to all internal regulators, analog and logic circuit blocks. the vdd supply is used for setting communication threshold levels and supplying power to the so driver. this ic architecture provides low quiescent current sleep modes. applying vpwr to the device will cause a power on reset (por). the on-chip oscillator supports the selectable pwm frequency and duty cycle. the on-chip voltage regulator and bandgap supply the required voltages to the internal circuitry. mcu interface and output control the device is designed with si x flexible pwm gate driver outputs. each driver may be cont rolled directly from the mcu and may be programmed through the spi for a specific frequency and duty cycle. low?side drivers: out1 ? out8 the 33800 provides flexible control of 8 low side driver outputs. outputs 1 and 2 are spec ifically designed with higher current limits to accommodate lamp inrush current. the device allows for parallel contro l of the outputs or spi control through the use of several input command words. constant current low side drivers: ccd1 and ccd2 the ccd1/ccd2 constant current controllers are switching hysteretic current controllers with a superimposed dither. the controllers are designed to provide a programmable constant current through a solenoid valve. fluid flow is controlled by the amount of current run through the driven solenoid valve. gate pre-drivers: gd1 ? gd6 the gd1 ? gd6 pins are the gat e drive outputs for external mosfets. they can be pwm?ed with speed and duty cycle choices per the spi command registers. internal to the device is a gate to source resistor designed to hold the external mosfet in the off state while the device is in por.
analog integrated circuit device data freescale semiconductor 19 33800 functional device operation operational modes functional device operation operational modes power supply the 33800 is designed to operate from 5.0 to 36v on the vpwr pin. the vpwr pin supplies power to all internal regulators, analog and logic circuit blocks. the v dd supply is used for setting communication threshold levels and supplying power to the so driver. this ic architecture provides flexible microprocessor interfacing with low quiescent current sleep modes. power-on reset (por) applying v pwr , v dd and en to the device will cause a power on reset (por) and place the device in normal or default mode. command register settings from power-on reset (por) via v pwr or v dd are as follows: ? all outputs off ? inputs enabled and or?d with spi bit. ? pwm frequency and duty cycle control disabled. ? oss open load detect current enabled. ? oss outputs with individual control. ? control inputs p1,p3,p5,p 7 enabled and or?d with the spi bit. ? ccd1 output off, diagnostic pull-up enabled, dac = 0. ? ccd2 output off, diagnostic pull-up enabled, dac = 0. power on reset circuit incorporates a 0.5 s timer to prevent high frequency transie nts from causing a por. during the low-voltage condition, internal logic states are maintained. to guarantee a por from v pwr , the vpwr pin must be less than 0.2v for greater than 1.0 s. modes of operation the 33800 has three operating modes, normal, sleep and default mode. a discussion on normal mode follows. normal mode normal mode allows full functional control of the device. transferring from sleep mode to normal mode performs a por and resets all internal registers to the por state. when entering normal mode from default mode, no por is performed and register states are maintained. features programmed in normal mode are listed below. further explanation of each feat ure is provided in subsequent paragraphs. ? programmable pwm frequency & duty cycle ? programmable pwm drain fault threshold ? ccd2 constant current dit her frequency and amplitude ? ccd2 dac programming ? ccd1 constant current dit her frequency and amplitude ? ccd1 dac programming ? on/off oss open load detect current ? calibration of timers ( calibration command ) ?reset ( reset command ) ? no operation ( no_op command ) default mode the default mode allows the user to disable all outputs except the pwm pre-driver. in default mode the pwm pre- driver outputs may only be controlled via the pwm input pins. all register control bits and fault bits are maintained in default mode, however control for the pre-driver is accomplished through the pwm pins only. with the default pin high, the device is placed in default mode. when exiting de fault mode, output control reverts to the internal register settings. in default mode the device operates with the following parameters. 1. oss outputs are disabled. 2. ccd1 and ccd2 outputs are disabled. 3. spi on/off control of gate drive (gd1 to gd6) outputs is disabled. pwmx input control is enabled. the device will operate as programmed prior to default mode. in default mode the device retains all register information and output status information . normal operation will resume when the default pin transitions low again. sleep mode sleep mode is entered by placing a logic [0] on the enable or vdd pins. all outputs are commanded off and the device enters a low quiescent current state. table 5. modes of operation v pwr v dd enable default mode l x x x power off h l x x sleep h h l x sleep h h h l normal h h h h default
analog integrated circuit device data 20 freescale semiconductor 33800 functional device operation logic commands and registers logic commands and registers spi and mcu interface description the 33800 device directly interfaces to a 3.3 or 5.0v microcontroller unit (mcu) us ing 16 bit serial peripheral interface (spi) protocol. spi serial clock frequencies up to 4.0mhz may be used when programming and reading output status information (production tested at 1mhz). figure 6 illustrates the serial peripheral interface (spi) configuration between an mcu and one 33800. command data is sent to the 33800 device through the si input pin. as data is being clo cked into the si pin, status information is being clocked out of the device by the so output pin. the response data received by the mcu during spi communication depends on the previous spi message sent to the device. the next so response data is listed at the bottom of each command table ( table 7, on page 22 , table 12, on page 25 , table 22, on page 30 table 23, on page 31 , table 26, on page 34 . spi integrity check checking the integrity of the spi communication with the initial power-up of the vdd and en pins is recommended. after initial system start-up or reset, the mcu will write one 32-bit pattern to the 33800. the first 16-bits read by the mcu will be the fault status (so me ssage 1) of t he outputs. the second 16-bits will be the same bit pattern sent by the mcu. by the mcu receiving the same bit pattern it sent, bus integrity is confirmed. the second 16-bit pattern the mcu sends to the device is the a command word and will be operated on by the device accordingly on rising edge of cs . important a sclk pulse count strategy has been implemented to ensure integrity of spi communications. spi messages consisting of 16 sclk pulses and multiples of 8 clock pulses thereafter will be acknowledged. spi messages consisting of other than 16 + mu ltiples of 8 sclk pulses will be ignored by the device. figure 6. spi interface with microprocessor two or more 33800 devices may be used in a module system. multiple ics may be spi-configured in parallel or serial. figures 7 and 8 show the configurations. when using the serial configuration, 32-clock cycles are required to transfer data in / out of the ics. figure 7. spi parallel interface with microprocessor figure 8. spi serial interface with microprocessor programmable pwm gate driver outputs the 33800 device is designed with six flexible pwm gate driver outputs. each driver may be controlled directly from the mcu or may be programmed thr ough the spi for a specific frequency and duty cycle. the pre-drivers are designed with four diagnostic features: 33800 microcontroller receive buffer parallel ports to logic 16-bit shift register shift register mosi si miso so sclk cs parallel ports microcontroller 33800 33800 si sclk cs si so sclk cs sclk miso mosi shift register so parallel ports microcontroller 33800 33800 si sclk cs si so sclk cs so sclk miso mosi shift register
analog integrated circuit device data freescale semiconductor 21 33800 functional device operation logic commands and registers ? off state open load detect ? on state short circuit detect ? programmable drain threshold and timer for short fault detection ? load resistance measurement each pre-driver is capable of detecting an open load in the off state and shorted load in t he on state. all faults are reported through spi communication. for open load detection, a resistor is placed between the drain sense pin and source sense pin of the ic. an open load fault is reported when the drain voltage is less than the 2.5v threshold. a shorted load fault is reported when the drain voltage is greater than the programm ed threshold voltage. programming of the drain shor t fault threshold voltage is done through spi commands provided in table 7 . bits 6 through 9 are used to perform the load resistance measurement function as described in the gate drive on/off command section below. gate drive on/off command the gd on/off command prov ides control bits for two functions: ? on/off control of the gdx outputs. ? load resistance measurement function. on/off control bit 0 through bi t 5 control gate drive outputs gd1 through gd6 respectively. setting the bit to logic1 will enable the gate drive to the exte rnal mosfet. setting the bit to logic 0 will actively pull the gate to ground. gd on/off command bits 6 through 9 control the load measurement feature. the ga te drive pre-drivers are selected in matched pairs. selecting a load resistance measurement disables a specif ied output pair and performs the resistance measurement using the defined pair. all other outputs will operate as program med. resistance is measured by passing a known current through the load and by measuring the voltage across it. the resistor placed on the rext pin determines the current through the load during measurement. the voltage outp ut on the lrfdbk pin is the differential load voltage with the defined current through it. from the two parameters, the load resistance may be calculated. table 6 illustrates the load diagnostic multiplex function. pwm pin enable command the pwm pin enable command provides control bits for two functions: ? enable or disable of pwm input pins. ? enable or disable of the internal pwm controller for gd1 through gd6. pwm pin enable bit 0 through bit 5 enable or disable the pwm1 through pwm6 input pins respectively. a logic 0 in the spi word will enable the pwm input pin, while logic 1 in the spi word will disable the pwm i nput pin. default state is with the pwm input pin enabled. with the pwm input pin disabled, the and/or function is also disabled and control is achieved through the gate drive on/off command or the internal pwm controller. and /or command the and/or command provides control bits for two functions: ? determines and/or relation between on/off spi bit and pwm input pin. ? enable or disable of the internal pwm controller for g1 through gd6. the and /or command describes the condition by which the pwm input pin controls the output driver. a logic[0] in the and / or register will or the pwm input pin with the respective bit in the on/off r egister. likewise, a logic[1] in table 6. load resistance measurement select bits 9876 mux select 0000 normal operation 0001 v dsns1 to r ext , v dsns2 to diff-amp + 0010 v dsns2 to r ext , v dsns1 to diff-amp + 0011 v dsns3 to r ext , v dsns4 to diff-amp + 0100 v dsns4 to r ext , v dsns3 to diff-amp + 0101 v dsns5 to r ext , v dsns6 to diff-amp + 0110 v dsns6 to r ext , v dsns5 to diff-amp + 0111 normal operation 1000 normal operation 1001 normal operation 1010 v dsns2 to r ext , v dsns1 to diff-amp + 1011 v dsns3 to r ext , v dsns1 to diff-amp + 1100 v dsns4 to r ext , v dsns1 to diff-amp + 1101 v dsns5 to r ext , v dsns1 to diff-amp + 1110 v dsns6 to r ext , v dsns1 to diff-amp + 1111 normal operation
analog integrated circuit device data 22 freescale semiconductor 33800 functional device operation logic commands and registers the and / or register will and the pwm input pin with the respective bit in the on/off register. the and/or function is disabled when the pwm input pin is disabled. table 7. pwm command pwm commands control address command bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r ld load resistance measurement select gate drive on/off bit gdx on/off command 0 = off, 1 = on 0 1 0 0 1 x 0 0 0 0 0 0 0 0 0 0 pwm controller enable bit pwm pin enable bit pwm pin enable command 0 = pwmx pin enabled 1 = pwmx pin disabled 0 1 0 1 0 x x 0 pwm3 0 pwm2 0 pwm1 0 0 0 0 0 0 and/or command 0 = pwmx pin or with spi 1 = pwmx pin and with spi 0 1 0 1 1 x x 0 pwm6 0 pwm5 0 pwm4 0 0 0 0 0 0 command control address frequency select duty cycle select pwm1 freq & dc 0 1 1 0 0 x 0 0 0 0 0 0 0 0 0 0 pwm2 freq & dc 0 1 1 0 1 x 0 0 0 0 0 0 0 0 0 0 pwm3 freq & dc 0 1 1 1 0 x 0 0 0 0 0 0 0 0 0 0 pwm4 freq & dc 0 1 1 1 1 x 0 0 0 0 0 0 0 0 0 0 pwm5 freq & dc 1 0 0 0 0 x 0 0 0 0 0 0 0 0 0 0 pwm6 freq & dc 1 0 0 0 1 x 0 0 0 0 0 0 0 0 0 0 control address v dsns3 v dsns2 v dsns1 vdsns123 short threshold 1 0 0 1 0 x x 0 1 1 0 1 1 0 1 1 vdsns123 short timer 1 0 0 1 1 x x 0 1 1 0 1 1 0 1 1 control address v dsns6 v dsns5 v dsns4 vdsns456 short threshold 1 0 1 0 0 x x 0 1 1 0 1 1 0 1 1 vdsns456 short timer 1 0 1 0 1 x x 0 1 1 0 1 1 0 1 1 next so response (message 1) 0 = no fault, 1 = fault ovrvlt ,tlim or cal flt reset fault statu spw m6 fault statu spw m5 fault statu spw m4 fault statu spw m3 fault statu spw m2 fault statu spw m1 fault statu sout 8 fault statu sout 7 fault statu sout 6 fault statu sout 5 fault statu sout 4 fault statu sout 3 fault statu sout 2 fault statu sout 1
analog integrated circuit device data freescale semiconductor 23 33800 functional device operation logic commands and registers table 8. and/or/spi/parallel control pwm frequency/duty cycle command the pwm frequency/duty cycle command allows the user to individually program a pwm output with a frequency and duty cycle. once the pwm freq/dc registers are programmed, the pwm outpu t gd1, gd2, gd3 are controlled via the and/or command and gd4, gd5, gd6 are controlled via the pwm pin enable command. pre-driver output control bits supersede the internal pwm controller. gdx outputs must be commanded off for the controller to function. (see table 8 ) the duty cycle of the pwm output s is controlled by bits 0 through 6, inclusive. the duty cycle value is 1% per binary count from 1 to 100 with counts of 101 through 127 defaulting to 100%. for example: sending spi word; 01100x1110001100 this would set pwm1 output to 1.28khz frequency with a 12% duty cycle. table 9 defines the output frequency with the selected input bits. vdsnsx short th reshold command the short fault threshold voltage of the external mosfet may be programmed via spi. table 10 illustrates the bit pattern required for a particular short fault threshold. open load fault detect threshold is set internally to 2.5v and may not be programmed. vdsnsx short faul t timer command the short fault timer can be programmed via the spi to the values listed in table 11, on page 24 . when the 33800 detects an over-current condition, as defined by v ds exceeding the programmed short fault voltage threshold, the r load measure pwm pin en 0 = en 1 = dis and/or bit 0 = or 1 = and on/ off bit pwm freq/ dc en bit pwm pin output 0 x x x x x rload measure 0 1 x 0 0 x off 0 1 x 0 1 x freq/dc 0 1 x 1 x x on 0 0 0 0 0 0 off 0 0 0 0 1 0 freq/dc 0 0 0 x x 1 on 0 0 0 1 x x on 0 0 1 0 0 x off 0 0 1 x 0 0 off 0 0 1 0 1 x freq/dc 0 0 1 x 1 0 freq/dc 0 0 1 1 x 1 on table 9. frequency select frequency select bits 987 frequency hz 000 10 hz 001 20 hz 010 40 hz 011 80 hz 100 160 hz 101 320 hz 110 640 hz 111 1.28 khz notes: tolerance on selected frequency is +-10% with part calibrated. on state short faults may not be detected if t_on_short > 1/f_pwm * duty_cycle * 0.98.off state open faults may not be detected if t_off_open > 1/fpwm * (1-duty_cycle) * 0.75. table 10. vdsnsx fault threshold select pwm v ds flt bits 210 543 876 vdsnsx fault threshold select 000 0.5v 001 1.0v 010 1.5v 011 2.0 100 2.5v 101 3.0v 110 no change 111 no change
analog integrated circuit device data 24 freescale semiconductor 33800 functional device operation logic commands and registers 33800 will wait for the short faul t time period and then shut down the output drive, setting the fault status bit to a 1 in the serial output response register. example: load measurement operation to perform an accurate lo ad resistance measurement the 33800 device uses an alternate channel to determine a differential load voltage and forces a known load current. with the differential load voltage and the forced current the load resistance is calculated. as shown in table 6 , channel 2 is used as the battery refer ence for the load measurement of channel 1. the current through the channel 1 load is set by the external resistor. setting the resistance to 25 ? forces a current of 100ma. the meas urement is sampled within 200 s and is held for 150ms on the load resistance feedback (l rfdbk ) output. the differential amplifier has a fixed gain of 2.5v. hence for this example, a 10 ? load will produce a 2.5v output. when a second pair is selected for measurement, the sample and hold is reset and the measurement is immediately directed to the new load measurement. the previous pair immediately revert back to normal operation. figure 9. example of channel 1 measurement octal output driver (octal serial switch; oss) the 33800 provides flexible control of 8 low side driver outputs. outputs 1 and 2 are specifically designed with higher current limit to accommodate la mp inrush current. the device allows for parallel control and/or spi control through the use of several input command words. this section describes the logic operation and commands for the octal driver. the 33800 octal output driver message set consists of eight commands, and one response as shown in table 12 . bits 11 through 15 determine the specific command and bits 0 through 10 determine how a specific output will operate. the 33800 operates on the command word on the rising edge of cs . the most significant bit (msb) is sent and received first. note upon power-on reset all oss bits are defined as shown in table 12 . table 11. pwm short fault timer pwm flt timer bits 210 543 876 fault timer select 000 30 s 001 60 s 010 120 s 011 240 s 100 480 s 101 960 s 110 no change 111 no change notes: tolerance on fault timer setting is 10% with calibrated part. v pwr vdsns2 vssns123 gd2 gate drive control & diagnostics + ? rext lrfdbk predriver 2 + ? + ? vcal v pwr vdsns1 vssns123 gd1 predriver 1 differential amplifier gate drive control & diagnostics
analog integrated circuit device data freescale semiconductor 25 33800 functional device operation logic commands and registers on /off control command to program the 8 outputs of the 33800 on or off, a 16- bit serial stream of data is ente red into the si pin. the first 8- bits of the control word are used to identify the on / off command and the remaining 8-bits are used to turn on or off the specific output driv er. when commanding an output on or off, the most signif icant bit (msb) is sent and received first. bit 7 corresponds to output 8 down to bit 0 which corresponds to output 1. open load current enable command the open load enable command is provided to enable or disable the open load detect pull-down current. this feature allows the device to be used in led applications. on power up reset (por) or the reset command the pull-down current sources are disabled. to enable the open load current source, the user must program the open load current disable control register with logic[1]. open load faults may not be reported with the pull-down current source disabled. over-voltage shutdo wn/retry command the over voltage shutdown/ retry command allows the user to select the fault stra tegy for the outputs. the over- voltage control bit sets the operation of the outputs when returning from over-voltage. setting the over-voltage bit to logic[0] will force all outputs to remain off when v pwr returns to normal level. setting the over-voltage bit to logic[1] will command outputs to resume their previous state when v pwr returns to normal level. tlim command, timer command the tlim and timer commands are used to enhance the short circuit protection strategy of the octal serial switch output drivers. the timer protection scheme uses a low duty cycle in the event of a short circuit. the tl im protection circuit uses the table 12. oss spi control commands and response command control address command bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 oss on/off command 0 = off, 1 = on 0 0 0 0 1 x x x 0 0 0 0 0 0 0 0 open load current enable 0 = disable, 1 = enable 0 0 0 1 0 x x x 0 0 0 0 0 0 0 0 shutdown / retry from v pwr over voltage 0 = shutdown, 1 = retry 0 0 0 1 1 x x x 1 1 1 1 1 1 1 1 shutdown / retry from short circuit 0 = shutdown, 1 = retry 0 0 1 0 0 x x x 1 1 1 1 1 1 1 1 tlim command 0 = disable, 1 = enable 0 0 1 0 1 x x x 1 1 1 1 1 1 1 1 fault timer command 0 = fault timer disabled 1 = fault timer enabled 0 0 1 1 0 x x x 1 1 1 1 1 1 1 1 parallel outputs(7&8,5&6,3&4,1&2) parallel input pin enable 0 = individual control, px enabled 1 = parallel control, px disabled 0 0 1 1 1 x x x 0 output 7&8 0 output 5&6 0 output 3&4 0 output 1&2 0 p7 en 0 p5 en 0 p3 en 0 p1 en and/or control 0 = px pin or with spi 1 = px pin and with spi 0 1 0 0 0 x x x 0 0 0 0 0 0 0 0 next so response (message 1) 0 = no fault, 1 = fault ovrvlt ,tlim or cal flt reset fault statu spw m6 fault statu spw m5 fault statu spw m4 fault statu spw m3 fault statu spw m2 fault statu spw m1 fault statu sout 8 fault statu sout 7 fault statu sout 6 fault statu sout 5 fault statu sout 4 fault statu sout 3 fault statu sout 2 fault statu sout 1
analog integrated circuit device data 26 freescale semiconductor 33800 functional device operation logic commands and registers temperature of the out put driver to determine the fault. both methods may be selected or used individually. the following table provides an explanation of operation during fault condition. the low duty cycle used for the timer protection scheme is set by the fault timer used to detect the short circuit. for short circuits detected based on the output voltage exceeding the fault detection voltage threshold, the outputs will be turned off for the duration of the refresh timer (typically 10ms) and turned on for the duration of t he on-state short circuit fault timer (typically 500 s). for short circuits detected based on the output current exceeding t he output current limit, the outputs will be turned off for the duration of the refresh timer (typically 10 ms) and turned on for the duration of the current limit fault timer (typically 50 s). for off-state open load faults with retry timer enabled, the off-open fault is released and re-detected every 1-2 retry timer periods. retry timer for 1-2, 3-4, 5-6, and 7-8 are out of phase and may report a load present, if the oss read command cs is issued after the release, and before the re- detection (~500 s) of the off-st ate open load fault. table 13. tlim/timer control all oss outputs have a current limit control loop. current limit is always active in normal mode. current limit for out1 and out2 is 4.0 to 6.0a. cu rrent limit for out3 through out8 is 1.0 to 2.0a. parallel output, px pin enable command the parallel output command allows the user to parallel output for increased current ca pability and enables control of the px input pin. a logic 0 in the parallel output command provides individual control. logic 1 co mmands outputs to operate in parallel. for example, with bit 4 in the parallel output command a logic 1, outputs 1 & 2 are controlled together with the outputs paralleled, and the p1 pin enabled, a logic 1 on spi bit 0 or spi bit 1 will command both outputs on. similarly a logic 1 on the p1 pin will command both outputs on. px pin enable bit 0 through bit 3 enables or disables the p1, p3, p5, p7 pins respectively. a logic 0 in the spi word will enable the px input pin, while logic 1 in the spi word will disable the px input pin. default state is with the px input pins enabled. when paralleling output 1 & 2 the current limit is maintained at 4.0 to 6.0a. para llel current limit for drivers 3&4, 5&6, 7&8 is increased to a range of 2.0 to 4.0a. using a mosfet as output switches allows the connection of paired outputs. the r ds(on) of mosfet devices have inherent positive temperature coefficient providing balanced current sh aring between outputs without destructive operation. this mode of operation may be desirable in the event the application requires lower power dissipation or the added capa bility of switching higher currents. performance of para llel operation results in a corresponding decrease in r ds(on) , while the output current limit increases correspondingly. output off open load detect current may increase based on how the output off open load detect is programmed. table 14. and/or/spi/parallel control shutdn retry bit tlim bit fault timer bit operation during short fault 1 0 x timer only, outputs will retry on period out1-8 = ~500us for short circuit faults, and 50us for current limit faults on, ~10ms off. 1 1 0 tlim only, outputs will retry on tlim hysteresis. 1 1 1 timer and tlim, outputs will retry on period and driver temperature below threshold. out1-8 = ~500us on, ~10ms off 0 0 x timer only, outputs will not retry on period out1-8 = ~500us on, off 0 1 0 tlim only, outputs will not retry on tlim hysteresis. 0 1 1 timer and tlim, outputs will not retry on period or tlim. out1-8 = ~500us on, off parallel en bit px pin en bit px pin and/ or bit spi bit 1 spi bit 0 output 1&2 1 0 x x 0 0 off 1 0 x x 0 1 on 1 0 x x 1 0 on 1 0 x x 1 1 on 1 1 0 1(or) 0 0 off 1 1 0 1(or) 0 1 on 1 1 0 1(or) 1 0 on 1 1 0 1(or) 1 1 on 1 1 0 0(and) x x off 1 1 x 0(and) 0 0 off 1 1 1 0(and) 0 1 on 1 1 1 0(and) 1 0 on 1 1 1 0(and) 1 1 on
analog integrated circuit device data freescale semiconductor 27 33800 functional device operation logic commands and registers and /or command the and/or command provides control bits for the following function: ? determines and/or relation between on/off spi bit and px input pin. the and /or command describes the condition by which the px input pin controls the ou tput driver. a logic[0] in the and / or register will or the px input pin with the respective bit in the on/off register. likewise, a logic[1] in the and / or register will and the px input pin with the respective bit in the on/off register. the a nd/or function is disabled when the px input pin is disabled. serial output (so) response register fault reporting is accomplished through the spi interface. all logic[1]s received by the mcu via the so pin indicate fault. all logic[0]s received by the mcu via the so pin indicate no fault. all fault bits are cleared on the positive edge of cs . so bits 15 to 0 represent the fault st atus of outputs 15 to 0. the timing between two write word s must be greater than 450 s to allow adequate time to sense and report the proper fault status. ccd1 constant current controller the ccd1 constant current controller is a switching hysteretic current controller with a superimposed dither. the controller is designed to provide a programmable constant current through a solenoid valve. fluid flow is controlled by the amount of current run through the solenoid valve. the master spi device sends 16 bit command words to the 33800 device (see table 15 ). the master device sets up the output current based on the ccd1 control command. the ic is capable of sinking an average output current from 0ma to 1075ma (without dither). if operating the device with dither, the dac + dither value must be less than 1075ma or greater than 0.0ma. commands outside of this command range will automatically lock out dither. programming the solenoid current begins by sending the ccd1 control command. the command consists of an control address, diagnostic pull up enable bit (diag_pu_en), dither disable bi t (dthr_dis), and a 9-bits of data for digital to analog conversion (dac). the data is received and the dac provides bias for a comparator to produce a threshold level. the comparator drives a switch control circuit which generates a frequency modulated signal for the output drive. the differential voltage across the sense resistor provides the feedback necessary to maintain the desired output current. the outp ut current is continuously monitored as a differential vo ltage across the internal sense resistor. when the current is in recirculation and the driver is in the off state, the current will decay to the lower limit switch point. when the current reaches the lower limit, the driver will turn on to increase the current until the upper limit switch point is reached. the output current will continue to switch between the switch points, resulting in the desired average current. the switch points ar e set to a fixed 5% of the commanded current. the switching frequency and accuracy are dependent upon the load inductance and resistance, battery voltage, dit her amplitude and frequency, switch points and the commanded current. current dither is a method by which the average current is increased and decreased through the solenoid valve. the 33800 allows the user to program the frequency and amplitude of the dither c ontrol. dither amplitude is implemented by increasing and decreasing the dac by the programmed dither value. the rate at which the value changes is set by the progra mmed dither frequency. when reprogramming the dither amplit ude or dither frequency, the update will occur on the start of a positive cycle. the maximum value of the output (dac + dither) must be less than 1075ma. when a grea ter value is programmed the device will disable the dither on the output. similarly, the minimum value of the output (d ac - dither) must be greater than 0.0ma. requesting a lower value will disable the dither on the output. on/off control bit the ccd1 output may be used as a standard 1.0a low side driver. for on/off control, the ccd1_dis bit int the ccd1frequency & amplitude command must be set to logic 1. this disables the constant current driver and enables the on/off control. to turn the driver on a logic 1 is placed in the on/off control bit. a logic 0 pl aced in the on/off control bit will turn the driver off. the protection scheme in low side driver mode operates the same as constant current mode.
analog integrated circuit device data 28 freescale semiconductor 33800 functional device operation logic commands and registers ccd2 constant current controller the ccd2 constant current controller is a switching hysteretic current controller with a superimposed dither. the controller is designed to provide a programmable constant current through a solenoid valve. by controlling current through the solenoid valve, fluid flow control is achieved. the master spi device send s 16-bit command words to the 33800 device (see table 18 ). the master device sets up the output current based on the ccd2 control command. the ic is capable of sinking an average output current from 0.0ma to 232ma (without dither). if operating the device with dither, the dac + dither value must be less than 232ma or table 15. ccd1 constant curr ent controll er commands command control address command bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ccd1 command address diag pull up dthr dis 9 bit dac command data ccd1 control 0 = pull down current source 1 = pull up current source 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 ccd1 command address ccd1 retry on/ off ccd1 dis tlim en dither amplitude dither frequency ccd1 frequency & amplitude 1 0 1 1 1 1 0 0 1 0 1 1 0 1 0 0 next so response (message 2) 0 = no fault, 1 = fault ovrvlt tlim or cal flt reset trim set (19) vcal status int=0 ext=1 open fault ccd2 short fault ccd2 open fault ccd1 short fault ccd1 fault status out8 fault status out7 fault status out6 fault status out5 fault status out4 fault status out3 fault status out2 fault status out1 notes 19. trim set bit indicates (0=untrimmed, 1= trimmed) 20. vcal status bit indicates when internal or external supply is used. vcal bit = 0 indicates ex ternal, vcal bit = 1indicates i nternal. 21. reset bit indicates the device has performed a por. 22. ccd1 disable bit allows the ccd1 driver to operate as a st andard 1.0a low side driver. with ccd1_dis bit = 1 the ccd1 functi on is disabled. table 16. ccd1 dither frequency select bits 3210 dither frequency 0000 dither off 0001 50hz 0010 100hz 0011 150hz 0100 200hz 0101 250hz 0110 300hz 0111 350hz 1000 400hz 1001 450hz 1010 500 hz 1011 133hz 1100 166hz 1101 233hz 1110 266hz 1111 no change notes: frequencies above 250hz are +- 20% table 17. ccd1 dither amplitude select bits 654 dither amplitude 000 dither off 001 50.4ma 010 100.8ma 011 151.2ma 100 201.6ma 101 252.0ma 110 302.4ma 111 352.8ma
analog integrated circuit device data freescale semiconductor 29 33800 functional device operation logic commands and registers greater than 0.0ma. commands outside of this command range will automatically lock out dither. programming the solenoid current begins by sending the ccd2 control command. the command consists of an control address, diagnostic pull-up enable bit (diag_pu_en), dither disable bit (dthr_dis), and a 9-bits of data for digital to analog conversion (dac). the data is received and the dac provides bias for a comparator to produce a threshold level. the comparator drives a switch control circuit which generates a frequency modulated si gnal for the output drive. the differential voltage across the sense resistor provides the feedback necessary to maintain the desired output current. the output current is continuously monitored as a differential voltage across the internal sense resistor. when the current is recirculation and the driver is in the off state, the current will decay to the lower limit switch point. when the current reaches the lower limit, the driver will turn on to increase the current until the upper limit switch point is reached. the output current will continue to switch between the switch points, resulting in the desired average current. the switch points are set to a fixed +/-5% of the commanded current. the switching frequency and accuracy are dependent upon the load induct ance and resistance, battery voltage, dither amplitude and frequency, switch points, and the commanded current. current dither is a method by which the average current is increased and decreased through the solenoid valve. the 33800 allows the user to program the frequency and amplitude of the dither c ontrol. dither amplitude is implemented by increasing and decreasing the dac by the programmed dither value. the rate at which the value is changed is set by the programmed dither frequency. when reprogramming the dither amplit ude or dither frequency, the update will occur on the start of a positive cycle. the maximum value of the output (dac + dither) must be less than 232ma. when a great er value is programmed, the device will disable dither on the output. similarly, the minimum value of the output (d ac - dither) must be greater than 0.0ma. requesting a lower value will disable dither on the output. table 18. ccd2 constant curre nt controller commands command control address command bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ccd2 command address diag pull- up dthr dis 9 bit dac command data ccd2 control 0 = pull-down current source 1 = pull-up current source 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ccd2 command address ccd2 retry dither amplitude dither frequency ccd2 frequency & amplitude 1 1 0 0 1 1 x x x 0 1 1 0 1 0 0 next so response (message 2) 0 = no fault, 1 = fault ovrvlt ,tlim or cal flt reset trim set (23) vcal status int=0 ext=1 open fault ccd2 short fault ccd2 open fault ccd1 short fault ccd1 fault status out8 fault status out7 fault status out6 fault status out5 fault status out4 fault status out3 fault status out2 fault status out1 notes 23. trim set bit indicates (0 = untrimmed, 1 = trimmed) 24. vcal status bit indicates when internal or external supply is used. vcal bit = 0 indicates external, vcal bit = 1indicates i nternal. 25. reset bit indicates the device has performed a por.
analog integrated circuit device data 30 freescale semiconductor 33800 functional device operation logic commands and registers calibration command in cases where an accurate time base is required, the user may calibrate the internal timers using the calibration command (refer to table 5 ) . after the 33800 device receives the calibration command, the device expects a 32 s logic[0] calibration pulse on the cs pin. the pulse is used to calibrate the internal clock. spi communication is allowed during calibration. because the osci llator frequency changes with temperature, calibration is required for an accurate time base. the calibration command may be used to update the device on a periodic basis. reset command the reset command resets all registers to power-on reset (por) state. refer to table 22 , on page 30 , for por states or the paragraph entitled power-on reset (por) on page 19 of this datasheet. . table 19. ccd2 dither frequency select bits 3210 dither frequency 0000 dither off 0001 50hz 0010 100hz 0011 150hz 0100 200hz 0101 250hz 0110 300hz 0111 350hz 1000 400hz 1001 450hz 1010 500hz 1011 133hz 1100 166hz 1101 233hz 1110 266hz 1111 no change notes: frequencies above 250hz are +- 20% - assumes part is calibrated table 20. ccd2 dither amplitude select bits 456 dither amplitude 000 dither off 001 21.8ma 010 32.7ma 011 43.6ma 100 54.5ma 101 65.4ma 110 75.3ma 111 87.2ma table 21. calibration command command control address command bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 calibration command 1 1 0 1 0 x x x x x x x x x x x table 22. reset command command control address command bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reset 1 1 0 1 1 x x x x x x x x x x x next so response (message 1) 0 = no fault, 1 = fault ovrvlt ,tlim or cal flt reset fault status pwm 6 fault status pwm 5 fault status pwm 4 fault status pwm 3 fault status pwm 2 fault status pwm 1 fault status out8 fault status out7 fault status out6 fault status out5 fault status out4 fault status out3 fault status out2 fault status out1
analog integrated circuit device data freescale semiconductor 31 33800 functional device operation logic commands and registers no operation command sending these two commands perform no operation. the device outputs will remain in previous state. . fault operation on each spi communication, a 16-bit command word is sent to the 33800 and a 16-bit status word is received from the 33800. the most significant bit (msb) is sent and received first. command register definition: 0 = output command off 1 = output command on so definition: 0 = no fault 1 = fault spi command summary table 25 below provides a comprehensive list of spi commands recognized by device 33800 and the reset state of each register. table 23. no operation command command control address command bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 no operation 1 1 1 1 1 x x x x x x x x x x x no operation 0 0 0 0 0 x x x x x x x x x x x next so response (message 1) 0 = no fault, 1 = fault ovrvl t,tli m or cal flt reset fault statu spw m6 fault statu spw m5 fault statu spw m4 fault statu spw m3 fault statu spw m2 fault statu spw m1 fault statu sout 8 fault statu sout 7 fault statu sout 6 fault statu sout 5 fault statu sout 4 fault statu sout 3 fault statu sout 2 fault statu sout 1 table 24. fault operation serial output (so) pin reports over-current so pin reports short-to-battery /supply or over-current condition. output on open load fault not reported on gdx and outx outputs. reported on ccd1 and ccd2 outputs output off open load fault so pin reports output ?off? open load condition. device shutdowns over-voltage total device shutdown at v pwr = 36.5 to 44v. resumes normal operation with proper voltage. upon recovery all outputs assume previous state or off based on the over-voltage bit in the shutdown / retry control register. over-current outx & ccdx outputs will remain in current limit until t sc limit is reached. with tlim enabled, outx & ccdx outputs will remain in current limit until tlim is reached. table 25. spi commands command name control address command bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 miscellaneous common commands calibration command 1 1 0 1 0 x x x x x x x x x x x
analog integrated circuit device data 32 freescale semiconductor 33800 functional device operation logic commands and registers reset 1 1 0 1 1 x x x x x x x x x x x no operation 1 1 1 1 1 x x x x x x x x x x x no operation 0 0 0 0 0 x x x x x x x x x x x oss commands oss x commands out 8 out 7 out 6 out 5 out 4 out 3 out 2 out 1 oss on/off 1 = on, 0 = off 0 0 0 0 1 x x x 0 0 0 0 0 0 0 0 open load current enable 0 = enable, 1 = disable 0 0 0 1 0 x x x 0 0 0 0 0 0 0 0 shutdown / retry from v pwr over-voltage 0 = shutdown, 1 = retry 0 0 0 1 1 x x x 1 1 1 1 1 1 1 1 shutdown / retry from short circuit 0 = shutdown, 1 = retry 0 0 1 0 0 x x x 1 1 1 1 1 1 1 1 tlim enable 1 = enable, 0 = disable 0 0 1 0 1 x x x 1 1 1 1 1 1 1 1 fault timer enable 1 = enable, 0 = disable 0 0 1 1 0 x x x 1 1 1 1 1 1 1 1 parallel outputs enable (7&8,5&6,3&4,1&2) 0 = individual control 1 = parallel control px pin enable 0 = enable px 1 = disable px (spi only) 0 0 1 1 1 x x x 1 out 7 & 8 1 out 5 & 6 1 out 4 & 3 1 out 2 & 1 0 p7 en 0 p5 en 0 p3 en 0 p1 en and/or control 1 = px pin and with spi 0 = px pin or with spi 0 1 0 0 0 x x x 0 0 0 0 0 0 0 0 table 25. spi commands command name control address command bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
analog integrated circuit device data freescale semiconductor 33 33800 functional device operation logic commands and registers gdx commands r ld load resistance measurement select gate drive on/off bit gdx on/off command 0 = off, 1 = on 0 1 0 0 1 x 0 0 0 0 0 0 0 0 0 0 pwm controller enable bit pwm pin enable bit pwm pin enable command 0 = pwmx pin enabled 1 = pwmx pin disabled 0 1 0 1 0 x x 0 pwm3 0 pwm2 0 pwm1 0 0 0 0 0 0 and/or command 0 = pwmx pin or with spi 1 = pwmx pin and with spi 0 1 0 1 1 x x 0 pwm6 0 pwm5 0 pwm4 0 0 0 0 0 0 frequency select duty cycle select pwm1 freq & duty cycle 0 1 1 0 0 x 0 0 0 0 0 0 0 0 0 0 pwm2 freq & duty cycle 0 1 1 0 1 x 0 0 0 0 0 0 0 0 0 0 pwm3 freq & duty cycle 0 1 1 1 0 x 0 0 0 0 0 0 0 0 0 0 pwm4 freq & duty cycle 0 1 1 1 1 x 0 0 0 0 0 0 0 0 0 0 pwm5 freq & duty cycle 1 0 0 0 0 x 0 0 0 0 0 0 0 0 0 0 pwm6 freq & duty cycle 1 0 0 0 1 x 0 0 0 0 0 0 0 0 0 0 v dsns3 v dsns2 v dsns1 v dsns123 short threshold 1 0 0 1 0 x x 0 1 1 0 1 1 0 1 1 v dsns123 short timer 1 0 0 1 1 x x 0 1 1 0 1 1 0 1 1 v dsns6 v dsns5 v dsns4 v dsns456 short threshold 1 0 1 0 0 x x 0 1 1 0 1 1 0 1 1 v dsns456 short timer 1 0 1 0 1 x x 0 1 1 0 1 1 0 1 1 ccd commands diag en dthr dis 9 bit dac command data ccd1 control 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 ccd1 retry lsd on/ off ccd1 dis tlim en dither amplitude dither frequency ccd1 frequency & amplitude 1 0 1 1 1 1 0 0 1 0 0 0 0 0 0 0 diag en dthr dis 9 bit dac command data table 25. spi commands command name control address command bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
analog integrated circuit device data 34 freescale semiconductor 33800 functional device operation logic commands and registers ccd2 control 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 ccd2 retry x x x dither amplitude dither frequency ccd2 frequency & amplitude 1 1 0 0 1 1 x x x 0 0 0 0 0 0 0 tlim query command 1 1 1 0 0 x x x x x x x x x x x tlim query response (27) 1=tlim fault on: calibration error, freq. high: calibration error, freq. low: vpwr over-voltage 0 0 0 0 0 1 0 1 0 ccd1 0 oss7 0 oss6 0 oss5 0 oss4 0 oss3 0 oss2 0 oss1 0 oss0 0 1 unused commands invalid command 1 1 1 0 1 x x x x x x x x x x x invalid command 1 1 1 1 0 x x x x x x x x x x x notes 26. 1 = vpwr over-voltage and 0 = ok 27. 1 = 0 = ok table 25. spi commands command name control address command bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 table 26. serial output (so) response register next so response (message 1) 0 = no fault, 1 = fault ovrvlt, or tlim fault reset fault status pwm6 fault status pwm5 fault status pwm4 fault status pwm3 fault status pwm2 fault status pwm1 fault status out8 fault status out7 fault status out6 fault status out5 fault status out4 fault status out3 fault status out2 fault status out1 next so response (message 2) 0 = no fault, 1 = fault ovrvlt, or tlim fault reset trim set (28) vcal status int=0 ext=1 open fault ccd2 short fault ccd2 open fault ccd1 short fault ccd1 fault status out8 fault status out7 fault status out6 fault status out5 fault status out4 fault status out3 fault status out2 fault status out1 notes 28. trim set bit indicates (0 = untrimmed, 1 = trimmed)
analog integrated circuit device data freescale semiconductor 35 33800 typical applications introduction typical applications introduction output off open load fault an output off open load fault is the detection and reporting of an open load when the corresponding output is disabled (input bit programmed to a logic low state). the output off open load fault is detected by comparing the drain-to-source voltage of the s pecific mosfet output to an internally generated reference. each output has one dedicated comparator for this purpose. each output has an internal pull-down current source or resistor. the pull-down current sources are enabled on power-up and must be enabled for open load detect to function. in cases were the open load detect current is disabled, the status bit will always respond with logic 0. the device will only shut down the pull-down current in sleep mode or when disabled via the spi. during output switching, especi ally with capacitive loads, a false output off open load fault may be triggered. to prevent this false fault from being reported, an internal fault filter of 100 s to 450 s is incorporated. the duration for which a false fault may be reported is a function of the load impedance, r ds(on) , c out of the mosfet, as well as the supply voltage, v pwr . the rising edge of cs triggers the built- in fault delay timer. the timer must time out before the fault comparator is enabled to detect a faulted threshold. once the condition causing the open load fault is removed, the device resumes normal operation. the open load fault, however, will be latched in the output so response register for the mcu to read. under-voltage shutdown an under-voltage condition on v dd results in the global shutdown of all outputs and reset of all control registers. the under-voltage threshold is between 0.8 and 2.8v. an under-voltage condition on v pwr also results in the global shutdown of all outpu ts and reset of all control registers. the under-voltage threshold is between 3.0 and 4.4v low-voltage condition (4.4v< v pwr <9.0v) will operate per the command word, however status reported on so pin is not guaranteed and perf ormance may be out of specification limits. output voltage shutdown an over voltage condition on vdd (> 7.0) may result in permanent damage to the 33800. over-voltage on the vpwr pin will cause the 33800 to shut down until the voltage returns to a normal value. over voltage exceeding the maximum recommended voltage (45v) may cause permanent damage to the 33800. output voltage clamp each output of the 33800 incorporates an internal voltage clamp to provide fast turn-off and transient protection of each output. each clamp indep endently limits the drain-to- source voltage to 50v. the total energy clamped (e j ) can be calculated by multiplying the current area under the current curve (i a ) times the clamp voltage (v cl ) (see figure 10 ). characterization of the output clamps, using a single pulse non-repetitive method at 0. 3a, indicates the maximum energy to be 50mj at 150 c junction temperature per output. . figure 10. output voltage clamping reverse battery protection the 33800 device requires external reverse battery protection on the vpwr pin. all outputs consist of a power mosfet with an integral substrate diode. during reverse battery condition, current will flow through the load via the substrate diode. under this circumstance relays may energize and lamps will turn on. if load reverse battery protection is desired, a diode must be placed in series with the load. curren t area (i a ) clamp energy (e j = i a x v cl ) drain voltage time drain-to-source c lamp voltage (v cl = 45 v) dr ain cu rr e nt (i d = 0.3 a) gnd drain-to-source on voltage (v ds(o n) ) 50v) drain-to-source clamp voltage (v cl = 50v) drain-to-source on voltage (v ds(on) ) drain voltage clamp energy (e j = i a x v cl ) gnd time drain current (i d = 0.3a)
analog integrated circuit device data 36 freescale semiconductor 33800 packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the ?98a? listed below. ek (pb-free) suffix 54-pin soicw exposed pad 98asa99334d issue c
analog integrated circuit device data freescale semiconductor 37 33800 packaging package dimensions ek (pb-free) suffix 54-pin soic exposed pad 98asa99334d issue c
analog integrated circuit device data 38 freescale semiconductor 33800 revision history revision history revision date description of changes 1.0 7/2006 ? initial release 2.0 8/2006 ? updated format and style 3.0 7/2007 ? changed part number pc33800ek/r2 to mcz33800ek/r2 in ordering information. ? changed category from product preview to advance information. 4.0 8/2007 ? changed octal serial driver, output refresh timer, minimu m value from ?-? to 2.0ms on page 12 5.0 10/2007 ? added paragraph for pwm frequency/duty cycle command on page 23 ? revised table 12, oss spi commands and response on page 25 ? revised table 26, spi commands on page 31
mc33800 rev. 5.0 10/2007 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its produ cts for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically disclai ms any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specificati ons can and do vary in different applications and actual perf ormance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of ot hers. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized us e, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are t he property of their respective owners. ? freescale semiconductor, inc., 2007. all rights reserved. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

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